1. Field of the Invention
The present invention relates to window-based processing, and, more specifically but not exclusively, to windows of packet delay-offset values used in timing recovery in packet-based communication systems.
2. Description of the Related Art
This section introduces aspects that may help facilitate a better understanding of the invention. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
The goal for a receiver of a data signal in a data communication network that employs clock recovery is for the receiver to derive, from the received data signal, a clock signal representing the time domain of the data signal, so that the receiver can use the derived clock signal to process (e.g., recover the data from) the data signal. In physical layer-based clock-recovery systems, the clock signal is encoded in the data signal, which is transmitted as a single continuous stream of bit transitions (e.g., 1s and 0s). In addition, the timing nature of these bit transitions is preserved between the transmitter and receiver to create a single timing domain. The clock signal can then be recovered by exploiting the regularity of transitions between the 1s and 0s represented in the data signal. In packet-based systems, the data signal does not arrive at the receiver as a single continuous stream of 1s and 0s. The nature of packet-based systems is to transmit packets when data is available, resulting in a bursty exchange of packets between a transmitter and a receiver. In addition, the bits representing the packet data are synchronized to a local oscillator unique to each transmitter or receiver, creating multiple timing domains between the transmitter and receiver. In some packet-based systems in which the packets are transmitted by the transmitter at a relatively steady rate, it is possible to derive a clock signal from the times at which the packets arrive at the receiver.
Some packet-based data communication applications, such as circuit emulation services (CES), in which circuit-based signals are converted to packet-based signals for transmission and then reconverted back to circuit-based signals at the receiver, have relatively stringent timing requirements for the accuracy of the derived clock signal. One such timing requirement is controlled phase movement or the maximum time interval error (MTIE) limits of the derived clock signal for DS1 or E1 data signals. These stringent timing requirements can be difficult to satisfy in adaptive clock recovery packet-based communication systems in which the overall packet delay (i.e., the duration from the time that a packet leaves the transmitter until the time that the packet arrives at the receiver) can vary for a periodic sequence of transmitted packets due to such phenomena as network loading and path rerouting.
It is a known phenomenon in many data networks that the statistical packet-delay characteristics change as overall network load changes. Thus, the duration between the arrival times of consecutive packets at a receiver can vary unpredictably as network load varies over time. Furthermore, when the path selected for transmitting packets of a particular communication session from a particular transmitter (source) to a particular receiver (destination) changes, e.g., due to a network reconfiguration associated with intermediate node congestion, link failure, or maintenance activities, the time domain of the packets arriving at the receiver will experience a positive or negative step change (referred to herein as a “step-delay”), depending on whether the new path is longer or shorter (in terms of overall delay) than the old path. Clock recovery systems at receivers in such packet-based networks will typically need to take the effects of these phenomena into account in order to satisfy their relevant timing requirements.